The present invention relates to integrated circuit devices and, more particularly, integrated circuits including storage nodes and methods for manufacturing integrated circuit devices including a storage node of a capacitor.
Various integrated circuit devices, including semiconductor memory devices, include one or more capacitors fabricated (manufactured) on an integrated circuit substrate. There is a growing need to increase the capacitance within a limited area as integrated circuit (semiconductor) devices become more highly integrated. Various approaches have been proposed to provide a desired capacitance in a more limited space, for example, to provide increased density of memory cells in an integrated circuit memory device. One proposed approach is a thinning method for reducing the thickness of a dielectric layer. A second approach includes increasing the surface area of an electrode by using a three-dimensional electrode, such as cylinder-type electrode or a fin-type electrode. Another approach is to grow hemispherical grains (HSG) on the surface of an electrode. A further alternative approach is to use a dielectric layer having a dielectric constant which is significantly greater than that of a conventional oxide/nitride/oxide (ONO) dielectric.
For a polysilicon electrode, a low dielectric layer such as a Silicon Oxide (SION) layer, capable of suppressing a reaction between the polysilicon electrode and a dielectric layer may be beneficial in obtaining stable leakage current characteristics. This is because, if a high dielectric layer is used, a dielectric layer having low dielectric constant may be generated between the high dielectric layer and the polysilicon layer. This may deteriorate the performance of the resulting capacity or due to degradation of the net dielectric strength of the capacitor dielectric layer. As a result, the potential increase in capacitance value using the thinning method may be limited for polysilicon electrodes.
When a metal-insulator-metal (MIM) capacitor is formed using a dielectric layer made with a high dielectric material (such as Ta2O5 or BST((BA,Sr)TiO3) or ferroelectric materials having a high dielectric constant) as the dielectric layer, the capacitor is typically fabricated using an electrode formed of a metal rather than a conventional polysilicon electrode. For example, the capacitor electrode material may be selected from the group consisting of platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh) and osmium (Os), which typically do not react with the high dielectric layer but have high work function. In particular, ruthenium (Ru) may be easily etched by plasma containing oxygen, and thus is sometimes used an electrode of a MIM capacitor. As will be understood by those of skill in the art, the work function of a material is the minimum energy required to remove an electron from the Fermi level of the material into field-free space.
Storage nodes of a MIM capacitor can generally be classified into three types: a concave storage node, a cylindrical storage node and a stacked storage node. The stacked storage node generally has the most stable structure of these types of storage nodes and can generally be implemented with a finer (smaller) design rule than the other types of storage nodes. However, a stacked storage node may be difficult to manufacture, for example, because it may be hard to etch the metal used as the electrode of the stacked storage node.
It is known to form a dielectric layer having a contact plug therein on a semiconductor wafer in which a conductive region is formed during the manufacture of a stacked storage node. An etch stopper material layer and a sacrificial insulating material layer may subsequently be sequentially formed on the dielectric layer. Predetermined portions of the sacrificial insulating material layer and the etch stopper material layer may then be etched, thereby providing a structure including an etch stopper, a sacrificial dielectric layer, and a storage node hole exposing the contact plug.
After formation of the storage node hole, a relatively thick metal layer of a platinum group material is typically deposited on the integrated circuit substrate (semiconductor wafer), thereby filling the storage node hole, preferably completely. However, a void or seam may form in the metal layer in the storage node hole. As an increase of the capacitance of the stacked capacitor is typically provided by increasing the depth of the storage node hole relative to its diameter (i.e., its aspect ratio increases) it may be increasingly difficult to fill the storage node hole with the metal layer without forming a void or seam.
In a conventional manufacturing process, the metal layer deposited on the sacrificial dielectric layer is removed by etch back or chemical-mechanical polishing (CMP) after deposition to form a storage node in the storage node hole as the metal is not removed from the storage node hole by the removal process. The sacrificial dielectric layer is then removed and a dielectric layer and an upper electrode are sequentially formed on the integrated circuit device including the stacked storage node.
As a void or seam may form in the storage node of the conventional stacked capacitor storage node, the inner portion of the storage node typically may not be formed only of conductive materials. As a result, the storage node may be structurally weak and subject to being bent or deformed during a subsequent high-temperature heating process. In addition, the electrical characteristics of the storage node may deteriorate due to an increase in resistance.
A conventional process for fabricating a MIM capacitor having a ruthenium electrode will now be described with reference to FIGS. 1A and 1B. As shown in FIG. 1A, a first dielectric (interlevel insulating) layer 12, that includes a conductive contact plug 14, is formed on an integrated circuit (semiconductor) substrate 10. A second dielectric (mold oxide) layer 16 is deposited on the interlevel insulating layer 12. A portion of the mold oxide layer 16 is etched to define a storage node hole adjacent to (on) an exposed portion of the conductive plug 14. The storage node hole defines a lower electrode region 17. A conductive ruthenium layer 18 is deposited on the mold oxide layer 16 to fill the lower electrode region 17. As will be discussed below, however, a seam (void) 20 may result in the ruthenium layer 18 in the lower electrode region 17.
As shown in FIG. 1B, after deposition, the ruthenium layer 18 is polished to expose the surface of the mold oxide layer 16. As a result, the ruthenium layer 18 remains only in the lower electrode region 17 and defines a lower electrode (storage node) 18a. The remnant of the mold oxide layer 16 is removed as shown in FIG. 1B.
As also illustrated in FIG. 1B, a dielectric layer 22 is deposited to cover the lower electrode 18a and the interlevel insulating layer 12. A conductive layer, providing an upper electrode 25, is deposited that may fill the space between neighboring electrodes to provide a conventional MIM capacitor.
As seen in FIGS. 1A and 1B, such a conventional MIM capacitor may include defects. For instance, as the degree of integration of a integrated circuit device is increased, the size of the lower electrode region 17 is reduced, thereby increasing an aspect ratio of the resultant structure of the integrated circuit substrate 10. As a result, the ruthenium layer 18 may not completely fill the lower electrode region 17 and a relatively large seam 20 may result in the lower electrode 18a. The seam 20 may cause deformation of the lower electrode 18a during a subsequent process. Thus, the electrical characteristics of the MIM capacitor may be unstable. As shown in FIG. 1B, seams 20 are also formed in the upper electrode 25. More particularly, as the upper electrode 25 is generally forayed after depositing the dielectric layer 22, the aspect ratio of the resultant structure of the integrated circuit substrate 10 may become even greater and cause an undesirable number of seams 20 in the upper electrode 25.
One approach used in the prior art to reduce the problem of seams 20 in the lower electrode 18a is to thermally process (heat treat) the device at an elevated temperature after deposition of the ruthenium layer 18. As shown in FIG. 2, the heat treatment may reflow the ruthenium layer 18 and fill the seam 20. However, during the reflow of the ruthenium layer 18, the lower portion of the ruthenium layer 18, in contact with the conductive plug 14, may separate as the ruthenium flows to fill the seam 20. As a result, the quality of the contact between the ruthenium layer 18 and the conductive plug 14 may be reduced, such as by weakening the contact. The region designated “A” in FIG. 2 illustrates a region where the ruthenium layer 18 is separated from the conductive plug 14.